module cache_data_ram (
    input clk,
    input rst,
    input [9:0] idex,
    input we,
    input [127:0] write_cache_line_data,
    output [127:0] cache_line_data
);

reg [127:0] data_ram[0:1024];
integer i;

assign cache_line_data = data_ram[idex];

always @(posedge clk) begin
    if(rst) begin
        for(i=0;i<1024;i=i+1)
            data_ram[i] <= 'd0;
    end
    else begin
        if(we) begin
            data_ram[idex] <= write_cache_line_data;
        end
    end
        
end

endmodule //cache_data_ram